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ordering number : en6086 22299rm (ot) no. 6086-1/27 overview the lc75884e and LC75884W are 1/4 duty lcd display drivers that can directly drive up to 220 segments and can control up to four general-purpose output ports. these products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. features key input function for up to 30 keys (a key scan is performed only when a key is pressed.) 1/4duty - 1/2bias and 1/4duty - 1/3bias drive schemes can be controlled from serial data (up to 220 segments). sleep mode and all segments off functions that are controlled from serial data. segment output port/general-purpose output port function switching that is controlled from serial data. serial data i/o supports ccb format communication with the system controller. direct display of display data without the use of a decoder provides high generality. independent v lcd for the lcd driver block (v lcd can be set to in the range v dd -0.5 to 6.0 volts.) provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. res pin provided for forcibly initializing the ic internal circuits. rc oscillator circuit. package dimensions unit: mm qfp80e unit: mm sqfp80 0.15 1.6 14.0 17.2 0.8 124 25 40 41 64 65 80 21.6 0.8 3.0max 1.0 2.7 15.6 0.8 1.6 0.35 23.2 20.0 0.8 0.8 sanyo: qfp80e(qip80e) [lc75884e] 14.0 12.0 1.25 1.25 0.5 14.0 12.0 1.25 1.25 0.5 120 21 40 41 60 61 80 0.1 0.5 1.6max 1.4 0.5 0.2 0.135 sanyo: sqfp80 [LC75884W] lc75884e, LC75884W sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 1/4 duty lcd display drivers with key input function cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. ccb is a trademark of sanyo electric co., ltd. ccb is sanyo? original bus format and all the bus addresses are controlled by sanyo.
no. 6086- 2 /27 lc75884e, LC75884W parameter symbol conditions ratings unit maximum supply voltage v dd max v dd ?.3 to +7.0 v v lcd max v lcd ?.3 to +7.0 v in 1 ce, cl, di, res ?.3 to +7.0 input voltage v in 2 osc,test ?.3 to v dd +0.3 v v in 3 v lcd 1, v lcd 2, ki1 to ki5 ?.3 to v lcd +0.3 v out 1 do -0.3 to +7.0 output voltage v out 2 osc ?.3 to v dd +0.3 v v out 3 s1 to s55, com1 to com4, ks1 to ks6, p1 to p4 ?.3 to v lcd +0.3 i out 1 s1 to s55 300 a output current i out 2 com1 to com4 3 i out 3 ks1 to ks6 1 ma i out 4 p1 to p4 5 allowable power dissipation pd max ta = 85 c 200 mw operating temperature topr ?0 to +85 c storage temperature tstg ?5 to +125 c specifications absolute maximum ratings at ta=25 c, v ss =0v parameter symbol conditions ratings unit min typ max supply voltage v dd v dd 4.5 6.0 v v lcd v lcd v dd ?0.5 6.0 input voltage v lcd 1 v lcd 1 2/3 v lcd v lcd v v lcd 2 v lcd 2 1/3 v lcd v lcd input high level voltage v ih 1 ce, cl, di, res 0.8 v dd 6.0 v v ih 2 ki1 to ki5 0.6 v dd v lcd input low level voltage v il ce, cl, di, res, ki1 to ki5 0 0.2 v dd v recommended external resistance r osc osc 43 k recommended external capacitance c osc osc 680 pf guaranteed oscillator range f osc osc 25 50 100 khz data setup time t ds cl, di :figure 2 160 ns data hold time t dh cl, di :figure 2 160 ns ce wait time t cp ce, cl :figure 2 160 ns ce setup time t cs ce, cl :figure 2 160 ns ce hold time t ch ce, cl :figure 2 160 ns high level clock pulse width t h cl :figure 2 160 ns low level clock pulse width t l cl :figure 2 160 ns rise time t r ce, cl, di :figure 2 160 ns fall time t f ce, cl, di :figure 2 160 ns do output delay time t dc do r pu =4.7k , c l =10pf * 1 :figure 2 1.5 s do rise time t dr do r pu =4.7k , c l =10pf * 1 :figure 2 1.5 s allowable operating ranges at ta = ?0 to +85 c, v ss =0v note: * 1. since do is an open-drain output, these values depend on the resistance of the pull-up resistor r pu and the load capacitance c l .
no. 6086- 3 /27 lc75884e, LC75884W parameter symbol conditions ratings unit min typ max hysteresis v h ce, cl, di, res, ki1 to ki5 0.1 v dd v power-down detection voltage v det 2.5 3.0 3.5 v input high level current i ih ce, cl, di, res: v i = 6.0v 5.0 a input low level current i il ce, cl, di, res: v i = 0v ?.0 a input floating voltage v if ki1 to ki5 0.05 v dd v pull-down resistance r pd ki1 to ki5: v dd = 5.0v 50 100 250 k output off leakage current i offh do: vo = 6.0v 6.0 a v oh 1 ks1 to ks6: i o = ?00 a v lcd ?1.0 v lcd ?0.5 v lcd ?0.2 output high level voltage v oh 2 p1 to p4: i o = ?ma v lcd ?1.0 v v oh 3 s1 to s55: i o = ?0 a v lcd ?1.0 v oh 4 com1 to com4: i o = ?00 a v lcd ?1.0 v ol 1 ks1 to ks6: i o = 25 a 0.2 0.5 1.5 v ol 2 p1 to p4: i o = 1ma 1.0 output low level voltage v ol 3 s1 to s55: i o = 20 a 1.0 v v ol 4 com1 to com4: i o = 100 a 1.0 v ol 5 do: i o = 1ma 0.1 0.5 v mid 1 com1 to com4: 1/2bias, i o = 100 a 1/2v lcd ?1.0 1/2v lcd + 1.0 v mid 2 s1 to s55: 1/3bias,i o = 20 a 2/3v lcd ?1.0 2/3v lcd + 1.0 output middle level voltage * 2 v mid 3 s1 to s55: 1/3bias, i o = 20 a 1/3v lcd ?1.0 1/3v lcd + 1.0 v v mid 4 com1 to com4: 1/3bias,i o = 100 a 2/3v lcd ?1.0 2/3v lcd + 1.0 v mid 5 com1 to com4: 1/3bias,i o = 100 a 1/3v lcd ?1.0 1/3v lcd + 1.0 oscillator frequency fosc osc: r osc = 43k , c osc = 680pf 40 50 60 khz i dd 1 v dd :sleep mode 100 i dd 2 v dd : v dd = 6.0v, output open,fosc = 50khz 270 540 current drain i lcd 1 v lcd : sleep mode 5 a i lcd 2 v lcd : v lcd = 6.0v, output open, 1/2bias, 200 400 fosc = 50khz i lcd 3 v lcd : v lcd = 6.0v, output open, 1/3bias, 120 240 fosc = 50khz electrical characteristics for the allowable operating ranges nete: * 2. excluding the bias voltage generation divider resistor built into v lcd 1 and v lcd 2. (see figure 1.)
figure 1 1. when cl is stopped at the low level figure 2 no. 6086- 4 /27 lc75884e, LC75884W 2. when cl is stopped at the high level
pin assignment no. 6086- 5 /27 lc75884e, LC75884W
block diagram no. 6086- 6 /27 lc75884e, LC75884W
no. 6086- 7 /27 lc75884e, LC75884W pin pin no. function active i/o handling lc75884e LC75884W when unused s1/p1 1 79 s2/p2 2 80 s3/p3 3 1 l l open s4/p4 4 2 s5 to s53 5 to 53 3 to 51 com1 54 52 com2 55 53 l l open com3 56 54 com4 57 55 ks1/s54 58 56 ks2/s55 59 57 o open ks3 to ks6 60 to 63 58 to 61 ki1 to ki5 64 to 68 62 to 66 h i gnd osc 75 73 i/o v dd ce 78 76 h i cl 79 77 i gnd di 80 78 i do 77 75 o open res 76 74 l i v dd test 74 72 this pin must be connected to ground. i v lcd 1 71 69 i open v lcd 2 72 70 i open v dd 69 67 v lcd 70 68 v ss 73 71 power supply connection. connect to ground. pin functions segment outputs for displaying the display data transferred by serial data input. the s1/p1 to s4/p4 pins can be used as general-purpose output ports under serial data control. common driver outputs the frame frequency fo is given by : fo = (f osc /512)hz. key scan outputs although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced cmos transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. the ks1/s54 and ks2/s55 pins can be used as segment outputs when so specified by the control data. key scan inputs these pins have built-in pull-down resistors. oscillator connection an oscillator circuit is formed by connecting an external resistor and capacitor at this pin. serial data interface connections to the controller. note that do, being an open-drain output, requires a pull-up resistor. ce :chip enable cl :synchronization clock di :transfer data do :output data s reset signal input res=low display off key scan disabled all key data is reset to low res=high display on key scan enabled however, serial data can be transferred when res is low. used for applying the lcd drive 2/3 bias voltage externally. must be connected to vlcd2 when a 1/2 bias drive scheme is used. used for applying the lcd drive 1/3 bias voltage externally. must be connected to vlcd1 when a 1/2 bias drive scheme is used. logic block power supply connection. provide a voltage of between 4.5 and 6.0v. lcd driver block power supply connection. provide a voltage of between vdd?.5 and 6.0v.
serial data input 1. when cl is stopped at the low level note: b0 to b3,a0 to a3 ........ ccb address dd ................................ direction data no. 6086- 8 /27 lc75884e, LC75884W
no. 6086- 9 /27 lc75884e, LC75884W 2. when cl is stopped at the high level note: b0 to b3,a0 to a3 ........ ccb address dd ................................ direction data ccb address ........ 42h d1 to d220 ............ display data s0,s1 .................... sleep control data k0,k1 .................... key scan output/segment output selection data p0 to p2 ................ segment output port/general-purpose output port selection data sc ........................ segment on/off control data dr ........................ 1/2 bias or 1/3 bias drive selection data
control data functions 1. s0, s1 : sleep control data these control data bits switch between normal mode and sleep mode and set the states of the ks1 to ks6 key scan outputs during key scan standby. note: this assumes that the ks1/s54 and ks2/s55 output pins are selected for key scan output. no. 6086- 10 /27 lc75884e, LC75884W control data mode osc oscillator segment outputs output pin states during key scan standby s0 s1 common outputs ks1 ks2 ks3 ks4 ks5 ks6 0 0 normal operating operating h h h h h h 0 1 sleep stopped l l l l l l h 1 0 sleep stopped l l l l l h h 1 1 sleep stopped l h h h h h h 2. k0, k1 : key scan output /segment output selection data these control data bits switch the functions of the ks1/s54 and ks2/s55 output pins between key scan output and segment output. x: don? care note: ksn(n=1 or 2) : key scan output sn (n=54 or 55): segment output control data output pin state maximum number of k0 k1 ks1/s54 ks2/s55 input keys 0 0 ks1 ks2 30 0 1 s54 ks2 25 1 x s54 s55 20 3. p0 to p2 : segment output port/general-purpose output port selection data these control data bits switch the functions of the s1/p1 to s4/p4 output pins between the segment output port and the general-purpose output port. note: sn(n=1 to 4): segment output port pn(n=1 to 4): general-purpose output port the table below lists the correspondence between the display data and the output pins when these pins are selected to be genera l-purpose output ports. for example, if the s4/p4 output pin is selected to be a general-purpose output port, the s4/p4 output pin will output a high l evel (v lcd ) when the display data d13 is 1, and will output a low level (vss) when d13 is 0. control data output pin state p0 p1 p2 s1/p1 s2/p2 s3/p3 s4/p4 0 0 0 s1 s2 s3 s4 0 0 1 p1 s2 s3 s4 0 1 0 p1 p2 s3 s4 0 1 1 p1 p2 p3 s4 1 0 0 p1 p2 p3 p4 output pin corresponding display data s1/p1 d1 s2/p2 d5 s3/p3 d9 s4/p4 d13
no. 6086- 11 /27 lc75884e, LC75884W however, note that when the segments are turned off by setting sc to 1, the segments are turned off by outputting segment off w aveforms from the segment output pins. sc display state 0 on 1 off 4. sc : segment on/off control data this control data bit controls the on/off state of the segments. dr drive scheme 0 1/3 bias drive 1 1/2 bias drive 5. dr : 1/2 bias or 1/3 bias drive selection data this control data bit switches between lcd 1/2 bias or 1/3 bias drive. display data and output pin correspondence note: this is for the case where the output pins s1/p1 to s4/p4, ks1/s54 and ks2/s55 are selected for use as segment outputs. output pin com1 com2 com3 com4 s1/p1 d1 d2 d3 d4 s2/p2 d5 d6 d7 d8 s3/p3 d9 d10 d11 d12 s4/p4 d13 d14 d15 d16 s5 d17 d18 d19 d20 s6 d21 d22 d23 d24 s7 d25 d26 d27 d28 s8 d29 d30 d31 d32 s9 d33 d34 d35 d36 s10 d37 d38 d39 d40 s11 d41 d42 d43 d44 s12 d45 d46 d47 d48 s13 d49 d50 d51 d52 s14 d53 d54 d55 d56 s15 d57 d58 d59 d60 s16 d61 d62 d63 d64 s17 d65 d66 d67 d68 s18 d69 d70 d71 d72 s19 d73 d74 d75 d76 s20 d77 d78 d79 d80 s21 d81 d82 d83 d84 s22 d85 d86 d87 d88 s23 d89 d90 d91 d92 s24 d93 d94 d95 d96 s25 d97 d98 d99 d100 s26 d101 d102 d103 d104 s27 d105 d106 d107 d108 s28 d109 d110 d111 d112 output pin com1 com2 com3 com4 s29 d113 d114 d115 d116 s30 d117 d118 d119 d120 s31 d121 d122 d123 d124 s32 d125 d126 d127 d128 s33 d129 d130 d131 d132 s34 d133 d134 d135 d136 s35 d137 d138 d139 d140 s36 d141 d142 d143 d144 s37 d145 d146 d147 d148 s38 d149 d150 d151 d152 s39 d153 d154 d155 d156 s40 d157 d158 d159 d160 s41 d161 d162 d163 d164 s42 d165 d166 d167 d168 s43 d169 d170 d171 d172 s44 d173 d174 d175 d176 s45 d177 d178 d179 d180 s46 d181 d182 d183 d184 s47 d185 d186 d187 d188 s48 d189 d190 d191 d192 s49 d193 d194 d195 d196 s50 d197 d198 d199 d200 s51 d201 d202 d203 d204 s52 d205 d206 d207 d208 s53 d209 d210 d211 d212 ks1/s54 d213 d214 d215 d216 ks2/s55 d217 d218 d219 d220
for example, the table below lists the segment output states for the s11 output pin. no. 6086- 12 /27 lc75884e, LC75884W display data output pin state (s11) d41 d42 d43 d44 0 0 0 0 the lcd segments for com1,com2,com3 and com4 are off. 0 0 0 1 the lcd segment for com4 is on. 0 0 1 0 the lcd segment for com3 is on. 0 0 1 1 the lcd segments for com3 and com4 are on. 0 1 0 0 the lcd segment for com2 is on. 0 1 0 1 the lcd segments for com2 and com4 are on. 0 1 1 0 the lcd segments for com2 and com3 are on. 0 1 1 1 the lcd segments for com2,com3 and com4 are on. 1 0 0 0 the lcd segment for com1 is on. 1 0 0 1 the lcd segments for com1 and com4 are on. 1 0 1 0 the lcd segments for com1 and com3 are on. 1 0 1 1 the lcd segments for com1,com3 and com4 are on. 1 1 0 0 the lcd segments for com1 and com2 are on. 1 1 0 1 the lcd segments for com1,com2 and com4 are on. 1 1 1 0 the lcd segments for com1,com2 and com3 are on. 1 1 1 1 the lcd segments for com1,com2,com3 and com4 are on. serial data output 1. when cl is stopped at the low level note: b0 to b3, a0 to a3ccb address 2. when cl is stopped at the high level note: b0 to b3, a0 to a3ccb address ccb address ...... 43h kd1 to kd30 ........ key data sa ........................ sleep acknowledge data note: if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data(sa) will b e invalid.
output data 1. kd1 to kd30 : key data when a key matrix of up to 30 keys is formed from the ks1 to ks6 output pins and the ki1 to ki5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. the table shows the relationship between those pins and the key data bits. when the ks1/s54 and ks2/s55 output pins are selected to be segment outputs by control data bits k0 and k1 and a key matrix of up to 20 keys is formed using the ks3 to ks6 output pins and the ki1 to ki5 input pins, the kd1 to kd10 key data bits will be set to 0. 2. sa : sleep acknowledge data this output data bit is set to the state when the key was pressed. also, while do will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. sa will be 1 in sleep mode and 0 in normal mode. sleep mode functions sleep mode is set up by setting s0 or s1 in the control data to 1. the segment outputs will all go low and the common outputs will also go low, and the oscillator on the osc pin will stop (it will be started by a key press). this reduces power dissipation. this mode is cleared by sending control data with both s0 and s1 set to 0. however, note that the s1/p1 to s4/p4 outputs can be used as general-purpose output ports according to the state of the p0 to p2 control data bits, even in sleep mode. (see the control data description for details.) no. 6086- 13 /27 lc75884e, LC75884W ki1 ki2 ki3 ki4 ki5 ks1/s54 kd1 kd2 kd3 kd4 kd5 ks2/s55 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30
2. in normal mode the pins ks1 to ks6 are set high. when a key is pressed a key scan is started and the keys are scanned until all keys are released. multiple key presses are recognized by determining whether multiple key data bits are set. if a key is pressed for longer than 800t(s) (where t= ) the lc75884e/w outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. after the controller reads the key data, the key data read request is cleared (do is set high) and the lc75884e/w performs another key scan. also note that do, being an open-drain output, requires a pull-up resistor (between 1 and 10 k ). no. 6086- 14 /27 lc75884e, LC75884W note: * 3. in sleep mode the high/low state of these pins is determined by the s0 and s1 bits in the control data. key scan output signals are not output from pins that are set low. 1 fosc key scan operation functions 1. key scan timing the key scan period is 384t(s). to reliably determine the on/off state of the keys, the lc75884e/w scans the keys twice and determines that a key has been pressed when the key data agrees. it outputs a key data read request (a low level on do) 800t(s) after starting a key scan. if the key data dose not agree and a key was pressed at that point, it scans the keys again. thus the lc75884e/w cannot detect a key press shorter than 800t(s).
no. 6086- 15 /27 lc75884e, LC75884W 3. in sleep mode the pins ks1 to ks6 are set to high or low by the s0 and s1 bits in the control data. (see the control data description for details.) if a key on one of the lines corresponding to a ks1 to ks6 pin which is set high is pressed, the oscillator on the osc pin is started and a key scan is performed. keys are scanned until all keys are released. multiple key presses are recognized by determining whether multiple key data bits are set. if a key is pressed for longer than 800t(s)(where t= ) the lc75884e/w outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. after the controller reads the key data, the key data read request is cleared (do is set high) and the lc75884e/w performs another key scan. however, this dose not clear sleep mode. also note that do, being an open-drain output, requires a pull-up resistor (between 1 and 10 k ). sleep mode key scan example example: s0=0, s1=1 (sleep with only ks6 high) multiple key presses although the lc75884e/w is capable of key scanning without inserting diodes for dual key presses, triple key presses on the ki1 to ki5 input pin lines, or multiple key presses on the ks1 to ks6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. therefore, a diode must be inserted in series with each key. applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. 1 fosc note: * 4. these diodes are required to reliable recognize multiple key presses on the ks6 line when sleep mode state with only ks6 high, as in the above example. that is, these diodes prevent incorrect operations due to sneak currents in the ks6 key scan output signal when keys o n the ks1 to ks5 lines are pressed at the same time.
com1 1/4 duty, 1/2 bias drive technique com2 com3 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are turned off. lcd driver output when only lcd segments corresponding to com1 are on lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1, com2 and com3 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are on. vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v vlcd vlcd1, vlcd2 0 v 1/4 duty, 1/2 bias waveforms no. 6086- 16 /27 lc75884e, LC75884W
no. 6086- 17 /27 lc75884e, LC75884W com1 1/4 duty, 1/3 bias drive technique com2 com3 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are turned off. lcd driver output when only lcd segments corresponding to com1 are on lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1, com2 and com3 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3 and com4 are on. vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v vlcd vlcd1 vlcd2 0 v 1/4 duty, 1/3 bias waveforms
voltage detection type reset circuit (vdet) this circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage vdet, which is 3.0v, typical. to assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage v dd rise time when the logic block power is first applied and the logic block power supply voltage v dd fall time when the voltage drops are both at least 1 ms. (see figure 3.) power supply sequence the following sequences must be observed when power is turned on and off. (see figure 3.) power on :logic block power supply(v dd ) on ? lcd driver block power supply(v lcd ) on power off:lcd driver block power supply(v lcd ) off ? logic block power supply(v dd ) off however, if the logic and lcd driver block use a shared power supply, then the power supplies can be turned on and off at the same time. system reset the lc75884e/w supports the reset methods described below. when a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. when the reset is cleared, display is turned on and key scanning become possible. 1. reset methods (1) reset at power-on and power-down if at least 1 ms is assured as the logic block supply voltage v dd rise time when logic block power is applied, a system reset will be applied by the vdet output signal when the logic block supply voltage is brought up. if at least 1 ms is assured as the logic block supply voltage v dd fall time when logic block power drops, a system reset will be applied in the same manner by the vdet output signal when the supply voltage is lowered. note that the reset is cleared at the point when all the serial data (the display data d1 to d220 and the control data) has been transferred, i.e., on the fall of the ce signal on the transfer of the last direction data, after all the direction data has been transferred. however, the above operations will be performed regardless of the state (high or low) of the res pin. if res is high, the reset will be cleared at the point the above operations are completed. on the other hand, if res is low, the system will remain in the reset period as long as res is not set high, even if the above operations are completed. (see figure 3.) no. 6086- 18 /27 lc75884e, LC75884W
(2) reset when the logic block power supply voltage is in the allowable operating range (v dd = 4.5 to 6.0v) the system is reset when the res pin is set low, and the reset is cleared by setting res pin high. 2. lc75884e/w internal block states during the reset period clock generator reset is applied and the base clock is stopped. however, the osc pin state (normal or sleep mode) is determined after the s0 and s1 control data bits are transferred. common driver, segment driver & latch reset is applied and the display is turned off. however, display data can be input to the latch circuit in this state. key scan reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. key buffer reset is applied and all the key data is set to low. ccb interface, control register, shift register since serial data transfer is possible, these circuits are not reset. no. 6086- 19 /27 lc75884e, LC75884W note: t1 3 1 [ms] (logic block power supply voltage v dd rise time) t2 3 0 t3 3 0 t4 3 1 [ms] (logic block power supply voltage v dd fall time)
no. 6086- 20 /27 lc75884e, LC75884W 3. output pin states during the reset period x: don? care note: * 5. these output pins are forcibly set to the segment output function and held low. * 6. when power is first applied, these output pins are undefined until the s0 and s1 control data bits have been transferred. * 7. since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 k is required. this pin remains high during the reset period even if a key data read operation is performed. output pin state during reset s1/p1 to s4/p4 l * 5 s5 to s53 l com1 to com4 l ks1/s54, ks2/s55 l * 5 ks3 to ks5 x * 6 ks6 h do h * 7
sample application circuit 1 1/2 bias (for use with normal panels) no. 6086- 21 /27 lc75884e, LC75884W note: * 8. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75884e/w is reset by the vdet. * 9. if the res pin is not used for system reset, it must be connected to the logic block power supply v dd . * 10. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 6086- 22 /27 lc75884e, LC75884W sample application circuit 2 1/2 bias (for use with large panels) note: * 8. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75884e/w is reset by the vdet. * 9. if the res pin is not used for system reset, it must be connected to the logic block power supply v dd . * 10. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 6086- 23 /27 lc75884e, LC75884W sample application circuit 3 1/3 bias (for use with normal panels) note: * 8. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75884e/w is reset by the vdet. * 9. if the res pin is not used for system reset, it must be connected to the logic block power supply v dd . * 10. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
no. 6086- 24 /27 lc75884e, LC75884W sample application circuit 4 1/3 bias (for use with large panels) note: * 8. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the lc75884e/w is reset by the vdet. * 9. if the res pin is not used for system reset, it must be connected to the logic block power supply v dd . * 10. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. notes on transferring display data from the controller the display data (d1 to 220) is transferred to the lc75884e/w in four operations. all of the display data should be transferred within 30 ms to maintain the quality of the displayed image.
notes on the controller key data read techniques 1. timer based key data acquisition (1) flowchart (2) timing chart t5: key scan execution time when the key data agreed for two key scans. (800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600t(s)) t7: key address (43h) transfer time t8: key data read time (3) explanation in this technique, the controller uses a timer to determine key on/off states and read the key data. the controller must check the do state when ce is low every t9 period without fail. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. the period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. 1 t = fosc no. 6086- 25 /27 lc75884e, LC75884W
no. 6086- 26 /27 lc75884e, LC75884W 2. interrupt based key data acquisition (1) flowchart (2) timing chart t5: key scan execution time when the key data agreed for two key scans. (800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600t(s)) t7: key address (43h) transfer time t8: key data read time 1 t = fosc
ps no. 6086- 27 /27 lc75884e, LC75884W (3) explanation in this technique, the controller uses interrupts to determine key on/off states and read the key data. the controller must check the do state when ce is low. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. after that the next key on/off determination is performed after the time t10 has elapsed by checking the do state when ce is low and reading the key data. the period t10 in this technique must satisfy the following condition. t10 > t6 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. this catalog provides information as of february, 1999. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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